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ds2282 t1 fdl controller/monitor stik ds2282 022798 1/22 features ? fully implements the fdl message format as de- scribed in the ansi document t1.4031989 ? fully implements the maintenance message protocol described in at&t tr 54016 (1986/89) ? provides highlevel monitor counts, namely: errored seconds severely errored seconds unavailable seconds ? important counts are stored in nonvolatile memory ? works in conjunction with the ds2283 enhanced t1 line card stik or ds2180a t1 transceiver ? simple serial port used to retrieve information and control operation ? can be used without an external controller ? connects to a standard 30pin single inline con- nector ? single +5v supply pin assignment vdd rlos rclk rpos rneg nc int prmxa drven rxd txd tlclk slip plb pas ub1ub2 ub3 ub4 b8zs rst nc gnd ub5ub6 llb psen tlink ncnc 12 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 (actual size) description the ds2282 completely controls the facility data link (fdl) as described in the bellcore document tr tsy000194 (extended superframe format interface specification december 1987) and the ansi docu- ment t1.4031989 (carrier to carrier installation ds1 metallic interface). it also implements the protocol that is described in the at&t publication tr 54016 (re- quirements for interfacing dte to services employing esf 1986/89). in addition it provides a number of im- portant performance parameters involved in monitoring t1 lines such as errored seconds, severely errored seconds, and unavailable seconds. downloaded from: http:///
ds2282 022798 2/22 overview the ds2282 completely controls the facility data link (fdl) in t1 environments. it can handle the fdl re- quirements outlined in american national standards institute (ansi) document t1.4031989 or those out- lined in the at&t publication tr 54016 (1986/89). re- covered data from a t1 line is clocked into the ds2282 via the rpos and rneg pins with the rclk signal. see figure 1. the ds2282 synchronizes to the incom- ing data stream and extracts the fdl. then, it will de- code the incoming messages on the fdl and properly create the fdl messages that must be transmitted. an asynchronous serial port is used to control the ds2282 and to retrieve data from it. the port is oper- ated at 19.2 kbps. access to the onboard registers is achieved through the serial port via the txd and rxd pins. an address can be assigned to this serial port. this allows a single external controller to communicate over a single bus to as many as 31 separate ds2282's. see figure 2. each ds2282 will listen for its address and only respond when it is asked to do so. most of the clearable registers in the ds2282 that either count error events or errored time intervals are recorded in onboard, nonvolatile memory. hence, in case of a lo- cal loss of power, these registers will maintain their counts. two typical applications of the ds2282 are shown in figures 3a and 3b. in these applications, the ds2282 is completely controlling the fdl as well as monitoring the t1 line. the ds2250 micro stik is used to configure the ds2282 and to extract any performance data that may be required. in these applications, the ds2250 is also used to control either the ds2283 enhanced t1 line card stik or the ds2180a t1 transceiver. the ds2282 can also be operated without an external controller. see hardware mode section and table 7. ds2282 block diagram figure 1 int (7) slip (13) fdl extractor performance report message unscheduled message maintenance message decoder sr synchronizer error detector performance report message unscheduled message maintenance message decoder nonvolatile memory ubr serial port controller reset transmit fdl timing user port vdd(1)gnd(23) txd(11) rxd(10) drven(9) ub1(16) ub2(17) ub3(18) ub4(19) ub5(24) ub6(25) rclk(3) rpos(4) rneg(5) tlclk(12) tlink(28) prmxa(8) rst(21) psen(27) pas(15) rlos(2) b8zs(20) llb(26) plb(14) downloaded from: http:///
ds2282 022798 3/22 multiple ds2282 connection scheme figure 2 re 75176 ds2282 75176 ds2282 75176 controller rs422 or rs485 bus rxd txd drven rposrneg rclk rpos rneg rclk rxd txd drven rd de ab re rd de ab re rd de ab t1 line #1 t1 line #31 downloaded from: http:///
tclkrclk ds2282 rxd txd p1.0 ds2250 micro stik 3wire synchronous serial port 2wire asynchronous serial port cs sdo sdi sclk ds2180a t1 transceiver txd rxd b8zs slip rclk rpos rneg tlclk tlink ds2282 022798 4/22 system application with ds2283 figure 3a slip cs received data transmit data ds2282 plb rclk rpos rneg tlclk tlink 3wire synchronous serial port 2wire asynchronous serial port ub1ub2 ub3 ub4 llb txd rxd len0len1 len2 tais lb sdo sdi sclk rxd txd p1.0 rtip rring ttip tring ds2283 enhanced t1 line card stik ds2250 micro stik b8zs t1 transmit and receive twisted pairs system application with ds2180a figure 3b downloaded from: http:///
ds2282 022798 5/22 pin description table 1 pin symbol type description 1 vdd positive supply . 5.0 volts. 2 rlos o receive loss of sync . indicates sync status; high when internal resync is in progress, low otherwise. 3 rclk i receive clock . 1.544 mhz clock input. all internal time intervals are derived from this clock. a clock must be applied to this pin or the ds2282 will not operate properly. 4 5 rpos rneg i receive bipolar data . sampled on falling edge of rclk. can be tied together to receive nrz data and disable bpv and b8zs detection circuit - 5 rneg t oge th er t o rece i ve nrz d a t a an d di sa bl e bpv an d b8zs d e t ec ti on c i rcu it - ry. 6 nc no connect . do not connect any signal to this pin. 7 int o interrupt . transitions low when bits in the status register (sr) change state or when an unscheduled message (t1.403) or request message (54016) is received. 8 prmxa o prm transmit active . transitions high when a performance report message (t1.403) or response message (54016) is being sent via tlink. ds2282 will transmit 27 flags before each messages. the prmxa pin will be high for the message and flags. 9 drven o serial port drive enable . driven high when the ds2282 is transmitting data via txd. can be used to enable an external line driver. tie this pin low to invoke 8bit communications via the serial port. 10 rxd i serial port receive . serial data input; data is input asynchronously at 19.2kbps. 11 txd o serial port transmit . serial data output; data is output asynchronously at 19.2kbps. 12 tlclk i transmit link clock . 4 khz demand clock for the fdl data. 13 slip i slip occurrence event . this edgetriggered pin should be held low for at least 10 m s when a slip occurs locally. if local slip indications are not available, this pin should be tied low to allow model #3 to be sent in 54016 mode. 14 plb o payload loopback . transitions high when the code word or message for payload loopback activate has been received; transitions low when the code word or message for payload loopback deactivate has been re- ceived. 15 pas i program address select . used to program the serial port address; ac- tive high. 1617 18 19 ub1ub2 ub3 ub4 o user bits 1 to 4 . each user bit can be independently configured either high or low via the ubr register. in hardware mode, tied high or low exter- nally to configure ds2282. 20 b8zs i b8zs enable . tie low to disable b8zs; tie high to enable b8zs. logically or'ed with the b8zs bit in the ubr register; tie low if the b8zs bit is to be used to select b8zs mode. 21 rst i reset . active high level will initiate a reset. contains an internal pull down resister. downloaded from: http:///
ds2282 022798 6/22 pin description type symbol 22 nc no connect . do not connect any signal to this pin. 23 gnd ground . 0.0 volts. 2425 ub5ub6 o user bits 5 to 6 . each user bit can be independently configured either high or low via the ubr register. in hardware mode, tied high or low exter- nally to configure ds2282. 26 llb o line loopback . transitions high when the code word for line loopback activate has been received; transitions low when the code word for line loopback deactivate has been received. this pin does not go active in a 54016 environment. 27 psen program store enable . used in conjunction with the rst pin to program the onboard nonvolatile memory. in normal applications, do not connect any signal to this pin. 28 tlink o transmit link data . fdl data to be transmitted; updated on the falling edge of tlclk. 29 nc no connect . do not connect any signal to this pin. 30 nc no connect . do not connect any signal to this pin. serial port operation the registers in the ds2282 are controlled via a two wire, asynchronous serial port. all but four of the regis- ters are readonly; ubr, par, lbcr, and tumr are write only. see tables 2 through 5. registers on the ds2282 are read from or written to one at a time. com- munication over the serial port to one of the registers normally consists of either three, four, or five bytes. (note: reads from the esicr, uasicr, besicr, se- sicr, or cslficr consists of 194 bytes: two written to the ds2282 and 192 read from the stik.) the first byte is always written to the ds2282 and is called the address byte. normally, all communications via the asynchro- nous serial port on the ds2282 are performed in 11bit bursts. see figure 4. there is a start bit which is al-ways a zero, followed by eight data bits (lsb first), fol- lowed by an extra bit which is a one in the address byte and a zero in the register and data bytes, followed fi- nally by a stop bit which is always a one. if the user wishes to eliminate the need for the extra bit in the serial port communications of the ds2282, then either the se- rial port address on the stik must be set to decimal 31 (how to set the serial port address on the ds2282 is de- scribed in ainitializing the address of the serial porto) or the drven pin (pin 9) must be tied permanently low. if the user ties drven low, then the address defaults to zero. ds2282 serial port communications figure 4 d0 d1 d2 d3 d4 d5 d6 d7 extra bit bit stop bit start (lsb) (msb) d0 d1 d2 d3 d4 d5 d6 d7 bit stop bit start (lsb) (msb) rxd 1 txdrxd 2 txd notes: 1. if the serial port is programmed for addresses between 0 and 30 decimal (inclusive) 2. if the serial port is programmed for address 31 decimal or if drven tied low downloaded from: http:///
ds2282 022798 7/22 address byte eb 0 0 0 a4a3a2a1a0 (lsb) (msb) eb extra bit. should always be set to one. a4 address bit 4. the msb of the serial port address. a3 address bit 3. a2 address bit 2. a1 address bit 1. a0 address bit 0. the lsb of the serial port address. the second byte is also always written to the ds2282 and is called the register byte. the register byte con- tains the address of the register that is to be either read from or written to. the msb in the register byte is the clear bit. the clear bit is used to clear a register after it has been read; hence, it can only be used in association with read registers. furthermore, only certain read reg- isters are clearable. see tables 1 and 2. typically, the only registers that can be cleared after reading are reg- isters that count events and/or errors. register byte cb 0 a5a4 a3a2 a1 a0 (lsb) (msb) cb clear bit. set to a one if register is to be cleared after reading. a5 address bit 5. the msb of the register address. a4 address bit 4. a3 address bit 3. a2 address bit 2. a1 address bit 1. a0 address bit 0. the lsb of the register address. the third through fifth bytes (third through 194th for five of the 54016 registers) are the data bytes. the third byte in the communication over the serial port may be either read from or written to the ds2282. bytes four and five are always read from the ds2282 since there are no write registers longer than one byte. when writ- ing data bytes to the ds2282, the extra bit must be set to zero and the extra bit will be set to zero by the ds2282 for transfers at txd. data is read from and written to the ds2282, least signif- icant bit first. also in multiple byte registers, the least significant byte is read first and the most significant byte is read last. as an example, if a ds2282 had been programmed for a serial port address of five (decimal) and the user wished to retrieve and clear the count in the bpv count regis- ter (bpvcr=09h), then the following transactions would occur: 1. the address byte with the extra bit set to one and the proper serial port address <100000101> wouldbe written to the ds2282, least significant bit first. 2. the register byte with the clear bit set to one and the proper register address for the bpvcr selected <100001001> would be written to the ds2282, least significant bit first. 3. the current value in the 24bit (3byte) bpvcr is read from the ds2282; the least significant bit in the least significant byte is read first and the most signifi- cant bit in the most significant byte is read last. 4. the bpvcr will automatically be reset to zero after the read is completed. the serial port communication on the ds2282 is han- dled by the onboard ds5000 soft microcontroller. the ds5000 is based on an 8051type architecture. the ds2282 utilizes the asynchronous mode 2 operation of an 8051like microcontroller. hence, each byte written to the ds2282 must be preceded by a start bit (0) and followed with a stop bit (1). see figure 4. the ds2282 will append start and stop bits to the bytes that it trans- mits back to an external controller via the txd pin. more information on mode 2 operation can be found in the ds5000 soft microcontroller user's guide. register description there are five sets of registers in the ds2282: the sta- tus register, the user register, the loopback control register, the t1.403 registers, and the 54016 regis- ters. see tables 2 through 6. the status register (sr), the user register (ubr), and the loopback control register (lbcr) are always available for access. ei- ther the t1.403 register set or the 54016 register set will be available depending on whether the ds2282 is pro- grammed via the ubr to operate in either t1.403 or 54016 environments, respectively. downloaded from: http:///
ds2282 022798 8/22 status register summary table 2 name addr 2,3 r/w clearable description sr 04 r yes status register . an 8bit register that reports alarm conditions. see astatus register.o user register summary table 3 name addr 2,3 r/w clearable description ubr 1 14 w no user bit register . an 8bit register that sets the position of the six available user bits. see auser register.o loopback control register summary table 4 name addr 2,3 r/w clearable description lbcr 35 w no loopback control register . an 8bit register that determines the actions of the plb and llb pins. seealoopback control.o software version and level register summary table 4a name addr 2,3 r/w clearable description swvr 1 3f r no software version register . an 8bit register that reports the ds2282 software version. swlr 1 3e r no software version level register . an 8bit register that reports the ds2282 software version level in two's complement format. t1.403 register set summary table 5 name addr 2,3 r/w clearable description crccr 1 08 r yes crc count register . a 16bit register that counts crc6 error events. bpvcr 1 09 r yes bpv count register . a 24bit register that counts bipo- lar violations. oofcr 1 0a r yes oof count register . a 16bit register that counts oof error events. fecr 1 0b r yes frame error count register . a 16bit register that counts errors in the fps framing pattern. esr 1 0c r yes errored second register . a 16bit register that counts es. sesr 1 0d r yes severely errored second register . a 16bit register that counts ses. uasr 1 0e r yes unavailable seconds register . a 16bit register that counts uas. prmr0prmr1 prmr2 prmr3 10 11 1213 rr r r nono no no performance report message registers . four 8bit registers that contain the prms that were received in the fdl in the last four seconds. rumr 18 r yes receive unscheduled message register . an 8bit register that reports unscheduled messages as they are received. downloaded from: http:///
ds2282 022798 9/22 name description clearable r/w addr 2,3 tumr 19 w no transmit unscheduled message register . an 8bit register that is used to send unscheduled messages. prmesr 1 1c r yes prm errored second register . a 16bit register that counts es as reported in the prm. prmsesr 1 1d r yes prm severely errored second register . a 16bit reg- ister that counts ses as reported in the prm. prmer 1 1e r yes prm error register . an 8bit register that counts prms that are received in error. par 1 1f w no prm address register . an 8bit register determines the action of the prm opening address. notes: 1. register is nonvolatile. 2. values indicated in hexadecimal format. 3. all registers read/written lsb first. status register (04) the status register (sr) reports alarms and events. the sr is always cleared when it is read by an external controller, hence the clear bit in the register byte does not need to be set. all of the bits in the sr operate in a alatchedo fashion. that is, once an event or alarm has occurred, the appropriate bit in the sr will remain set until the sr is read. all of the bits in the sr will be cleared when read unless the alarm condition still exists. also, except for the b8zsd bit, the int pin will be asserted (transitions low), indicating to an external con- troller that a bit in the sr has changed status. the int pin will return high as soon as the status register is ac- cessed. sr: status register (04) plb llb 16zd rcl ryel rlos b8zsd ais (lsb) (msb) plb payload loopback. set when payload loopback is active. llb line loopback. set when line loopback is active. will not go active in 54016 envi- ronments. 16zd sixteen zero detect. set when 16 con- secutive zeros are received. an indica- tion of a pulse density violation. rcl receive carrier loss. set when 192 con- secutive zeros have been received. ryel receive yellow alarm. set when 16 con- secutive 00ff hex codes have been re- ceived in the fdl. rlos receive loss of sync. set when the ds2282 loses synchronization. b8zsd b8zs detect. set when a b8zs code word is received; operates whether the ds2282 is set up for b8zs or not. does not affect int . ais alarm indication signal. set when an un- framed all one's signal is received. software version register the software version register (swvr) (3f) allows the user to display software version information. when accessed, the ds2282 software revision will be returned by the serial port. for example, the serial port will return 0bh for software version v11. software level register the software level register (swlr) (3e) allows the user to display software version level information. when accessed, the two's complement of the ds2282 soft- ware revision level will be returned by the serial port. if the returned value is negative, the software revision level is in abetao or prototype state. if positive, the soft- ware revision level is the production release. for exam- ple, the serial port will return 05h for production software version level v11.5 (fbh for abetao release). downloaded from: http:///
ds2282 022798 10/22 user register (14) the ds2282 contains a 6bit user port (pins ub1 to ub6). an external controller can independently set or clear these user bits via the user bit register (ubr). the ubr is also used to select whether the ds2282 is to operate in a t1.403 or a 54016 environment. if the 54016 bit is set to a one, then the ds2282 will operate in a 54016 fashion and the 54016 register set will be se- lected. if the 54016 bit is cleared (set to zero), then the ds2282 will operate in a t1.403 fashion and the t1.403 register set will be selected. operation in both modes simultaneously is not allowed. if the user accesses the opposite mode's register set, a value of 00h is returned. for example, 00h will be returned if the ds2282 is pro- grammed for tr54016 mode and the user reads address location 08h (crccr). the b8zs bit should be set to a one when the ds2282 is connected to t1 streams that include b8zs code words. the default for the ubr is 00 hex. ubr: user bit register (14) b8zs 54016 ub6 ub5 ub4 ub3 ub2 ub1 (lsb) (msb) b8zs b8zs select. logically or'ed with the b8zs pin. 54016 54016 select. set to a one in a 54016 en- vironment. ub6 user bit 6. sets or clears the ub6 pin. ub5 user bit 5. sets or clears the ub5 pin. ub4 user bit 4. sets or clears the ub4 pin. ub3 user bit 3. sets or clears the ub3 pin. ub2 user bit 2. sets or clears the ub2 pin. ub1 user bit 1. sets or clears the ub1 pin. 54016 register set summary table 6 name addr 2,3 r/w clearable description csr 20 r no current status register . an 8bit register that indicates unavailable signal state and plb status. esfeer 21 r no esf error event register . a 16bit register that accumu- lates esf error events. cit 22 r no current interval timer . a 16bit register that counts the number of seconds in the current 15minute interval. ciesr 23 r no current interval es register . a 16bit register that indi- cates the number of errored seconds in current 15minute interval. ciuasr 24 r no current interval uas register . a 16bit register that indi- cates the number of unavailable seconds in current 15min- ute interval. cibesr 25 r no current interval bes register . a 16bit register that indi- cates the number of bursty errored seconds in current 15minute interval. cisesr 26 r no current interval ses register . a 16bit register that indi- cates the number of severely errored seconds in current 15minute interval. cicslfr 27 r no current interval css & lofc register . a 16bit register that counts controlled slip seconds and loss of frame in current 15minute interval. the 8bit css count is in the lsb and the 8bit lofc count is in the msb. esicr 28 r no es interval count registers . a set of 96 16bit registers that contain the errored second counts for the previous 96 individual 15minute periods. most recent interval is read first. downloaded from: http:///
ds2282 022798 11/22 name description clearable r/w addr 2,3 uasicr 29 r no uas interval count registers . a set of 96 16bit registers that contain the unavailable second counts for the previous 96 individual 15minute periods. most recent interval is read first. besicr 2a r no bes interval count registers . a set of 96 16bit registers that contain the bursty errored second counts for the pre- vious 96 individual 15minute periods. most recent interval is read first. sesicr 2b r no ses interval count registers . a set of 96 16bit registers that contain the severely errored second counts for the pre- vious 96 individual 15minute periods. most recent interval is read first. cslficr 2c r no css & lofc interval count registers . a set of 96 16bit registers that contain the controlled slip and loss of frame counts for the previous 96 individual 15minute periods. the 8bit css count is the lsb and the 8bit lofc count is in the msb. most recent interval is read first. esdcr 2d r no es day count registers . a 16bit register that counts the number of errored seconds in the previous 24hour period. ueeer 36 r yes user esf error event register . 16bit register that mimics the esfeer for user access. uasdcr 2e r no uas day count registers . a 16bit register that counts the number of unavailable seconds in the previous 24hour period. besdcr 2f r no bes day count registers . a 16bit register that counts the number of bursty errored seconds in the previous 24hour period. sesdcr 30 r no ses day count registers . a 16bit register that counts the number of severely errored seconds in the previous 24hour period. cslfdcr 31 r no css & lofc day count registers . a 16bit register that counts the number of controlled slip seconds and loss of frames in the previous 24hour period. the 8bit css count is in the lsb and the 8bit lofc count is in the msb. vitr 32 r no valid interval total register . an 8bit register that indi- cates the number of valid 15minute intervals in the previous 24hour period. rmsr 33 r yes request message status register . an 8bit register that indicates which (if any) request message is being received. cr 34 w no control register . an 8bit register that selects which ad- dress the ds2282 will respond to. notes: 1. all of the registers in the ds2282 that count events will saturate at their maximum possible count; they do not roll over. for example, all the 16bit registers stop at a count of 65,535. they do not roll over to zero and continue counting. 2. values indicated in hexadecimal format. 3. all register read/written lsb first. downloaded from: http:///
* service mark of at&t communications ds2282 022798 12/22 t1.403 operation in order to properly operate on t1 lines running the fdl under the definition spelled out in the ansi document t1.403, the ds2282 must have the 54016 bit in the ubr set to zero (see auser registero). the ds2282 will de- code both the incoming performance report messages (prm) and unscheduled messages and provide them for the user. the ds2282 also collects data on bipolar violations (bpv), frame errors, crc6 errors, and out offrame errors (oof). the ds2282 combines the in- formation in these registers along with the indication of local slips via the slip signal to create prms that are transmitted once a second via the tlink signal. also, the user can instruct the ds2282 to transmit unsched- uled messages. for more information on the t1.403 definition, refer to the application note at1.403 fdl message overview.o monitor registers there are two sets of monitor registers. the first set helps support some of the monitoring requirements on t1 lines as spelled out in documents such as ta tsy000147 (ds1 rate digital service monitoring unit functional specifications october 1987), tr 62411 (accunet* t1.5 service description and interface spec- ifications december 1988), and the ccitt recom- mendation g.821. this set consists of three registers, the errored seconds register (esr), the severely er- rored seconds register (sesr), and the unavailable seconds register (uasr). unlike the first set of moni- tor registers which provides a count of conditioned data, the second set of monitor registers just provides raw data counts of events such as crc6 errors, bipolar violations, frame errors, and out of frame errors. the se- cond set of monitor registers consists of four registers: the crc count register (crccr), the bipolar violation count register (bpvcr), the frame error count reg- ister (fecr), and the out of frame count register (oofcr). all of the monitor registers are described be- low. esr: errored seconds register (0c) . a 16bit register that counts errored seconds (es). an es is any onesecond time interval with either a frame bit error, crc6 error, oof event, or controlled slip event. sesr: severely errored seconds register(0d) . a 16bit register that counts severely errored seconds (ses). a ses is any onesecond time interval with an oof error event and/or more than 320 crc6 errors in it. uasr: unavailable seconds register (oe) . a 16bit register that counts unavailable seconds (uas). a uas is the number of seconds between 10 consecu- tive ses events (inclusive) and 10 consecutive non ses events (exclusive). the ds2282 starts counting ses events when it receives the first one. if it counts ten sess in a row, then it increments the uasr by ten and decrements the es and ses by ten. counts in the esr and sesr are inhibited during unavailable seconds. once the ds2282 has begun counting unavailable se- conds, it begins counting nonses events. at the first nonses event, it begins counting errored seconds in a separate register that is not available to the user. if the ds2282 fails to count ten nonses events in a row, it clears both the nonses count and the register count- ing errored seconds during unavailable seconds. if it counts ten nonses events in a row, it will decrement the uasr by ten and will increment the esr by the count in the register counting errored seconds during unavailable seconds. also, when the ds2282 detects either an incoming alarm indication signal (ais) or re- ceive carrier loss (rcl), it will increment the uasr for each second either of these conditions exists. crccr: crc6 error count register (80) . a 16bit register that records crc6 error events. the ds2282 calculates crc6 on the incoming data. each time the calculation does not match the crc6 code word in the incoming esf data stream, then the crccr is incremented by one. bpvcr: bipolar violation count register (81) . a 24bit register that records bipolar violations (line code violations). bipolar violations are counted whether the synchronizer in the ds2282 is in sync (the rlos signal is low) or not. if the ds2282 is set up to receive b8zs code words, then b8zs code words are not counted as bipolar violations. fecr: frame error count register (83) . a 16bit register that records errors in the framing pat- tern sequence (fps). all individual bit errors in the fps pattern (001011) are recorded in the fecr. downloaded from: http:///
ds2282 022798 13/22 oofcr: out of frame count register (82) . a 16bit register that records out of frame (oof) error events. an oof error event occurs whenever 2 or more framing bits out of 6 in the fps are incorrect. an oof error event will cause the ds2282 to resynchronize to the incoming data stream. receive prm operation the ds2282 decodes the incoming fdl for scheduled performance report messages (prm). it automatically detects opening flags, deletes any stuffed zero bits that may be present, and it calculates crc16 on all the data between the opening and closing flags. the ds2282 normally only decodes the current second's data (octets 5 and 6). data from the previous three se- conds is abumpedo from prmr0 to prmr1 to prmr2 to prmr3 and finally out of available recall range. if the prm is received in error (crc check sum is incorrect), the message will be ignored. the ds2282 will keep track of errored prms and properly place the unerrored message when it is received. for example, if a prm is received that does not correspond to its crc check sum, then prmr0 will be set to all zeros indicating that an invalid message was received. if the next scheduled message is received correctly, then the data missed in the last scheduled message will be updated to prmr1. note: prmr0 to prmr3 are only updated if prms are received; if no valid or invalid prms are received, then both the se and fe bits in prmr0 to prmr3 will be set to one. prmr0: prm register 0 (10) prmr1: prm register 1 (11) prmr2: prm register 2 (12) prmr3: prm register 3 (13) plb sl lv se fe crc2 crc1 crc0 (lsb) (msb) plb payload loopback activated sl controlled slip (slip 1) lv line violation (bpv 1) se severely errored framing event (2 of 6 oof 1) fe frame sync bit error event crc2 see table below crc1 see table below crc0 see table below crc2 crc1 crc0 event 0 0 0 invalid 0 0 1 crc=0 0 1 0 crc=1 (g1) 0 1 1 1 crc 5 (g2) 1 0 0 5 crc 10 (g3) 1 0 1 10 crc 100 (g4) 1 1 0 100 crc 319 (g5) 1 1 1 crc 320 (g6) prm history registers there are three registers that keep track of the sched- uled prm and collect data on the receive performance of the remote end. the first two of these registers (prmesr and prmsesr) mock the monitor registers in the type of data that they report. es and ses are cal- culated off of the received prm data. the prm data is pulled from prmr3 since it has the highest probability of containing valid data. if prmr3 does not contain val- id data, then es and ses are not calculated. the third register (prmer) keeps a count of how many prms have been received in error. prmesr: prm errored seconds register (1c) . a 16bit register that counts errored seconds (es). an es is any one second time interval with either a frame bit error (fe or se=1) or crc6 error (g1 to g6=1). prmsesr: prm severely errored seconds register (1d) . a 16bit register that counts severely errored seconds (ses). a ses is any one second time interval with an oof error event (se=1) or more than 320 crc6 error events (g6=1). prmer: prm error register (1e) . an 8bit reg- ister that records the number of prms that have been received in error. a prm is considered to be received in error when the calculated crc does not match the in- coming crc word. transmit prm operation the ds2282 will automatically generate prms once a second to be included into the fdl for transmission to the remote end. it automatically pulls together all the downloaded from: http:///
ds2282 022798 14/22 necessary data to create a prm from both the monitor registers and from the slip signal. it creates the open- ing and closing flags as well as the address and control bytes. once the prm packet has been assembled, the ds2282 will generate crc16 and include it at the end of the prm. and finally, before the prm is sent, zeros are inserted to insure that none of the prm data ap- pears as a flag. receive unscheduled message operation the ds2282 decodes incoming unscheduled mes- sages as they are received. the ds2282 will report the received unscheduled message via the rumr when the message has been received for three consecutive times. this integration allows the ds2282 to operate properly even on high bit error rate lines. the rumr is cleared when read via the serial port. the int pin will be asserted (transitions low), indicating to an external con- troller that an unscheduled message has been received three consecutive times. the user may count incoming unscheduled messages by monitoring the int pin. the int pin will return high as soon as the rumr is ac- cessed. two output signals on the ds2282 will respond to cer- tain unscheduled messages. the plb (payload loop- back) signal will transition high if the code word for pay- load loopback activate (001010) is received three times. it will remain high until the ds2282 has received the payload loopback deactivate code word (011001) three times. the llb (line loopback) signal operates simi- larly. the llb signal will transition high when the ds2282 has received the code word for line loopback activate (000111) three times. it will remain high until the ds2282 has received the code word for line loopback deactivate (011100) three times. the user has the op- tion to control the plb and llb pins via the loopback control register (lbcr); see aloopback control regis- ter.o rumr: receive unscheduled message register (18) na na cw5 cw4 cw3 cw2 cw1 cw0 (lsb) (msb) na not assigned. could be any value when read. na not assigned. could be any value when read. cw5 msb of the receive unscheduled mes- sage code word. cw0 lsb of the receive unscheduled mes- sage code word. transmit unscheduled message operation the ds2282 will transmit outgoing unscheduled mes- sages. the ds2282 will continuously transmit the un- scheduled message described in tumr if enabled via the tum bit in the tumr. if unscheduled messages are being transmitted, all prms are superseded. when the tum is cleared, the ds2282 will finish sending the un- scheduled message that it is currently transmitting be- fore switching to either the idle code or prms. tumr: transmit unscheduled message register (19) tum 0 cw5 cw4 cw3 cw2 cw1 cw0 (lsb) (msb) tum transmit unscheduled message enable cw5 msb of the transmit unscheduled mes- sage code word. cw0 lsb of the transmit unscheduled mes- sage code word. par: prm address register (1f) . the ds2282 allows the user to set the prm opening address c/r bit depending on the source of the prm. the c/r bit is set to zero for prms created by user equipment such as a cpe or set to one for prms created by a carrier. the par allows the user to control the expected state of the c/r bit as well as control the state of the bit in the prms created by the ds2282. 0 0 0 0 0 0 tc/r rc/r (lsb) (msb) tc/r transmit prm c/r bit control 0=force c/r bit to zero in outgoing prm 1=force c/r bit to one in outgoing prm rc/r receive prm c/r bit control 0=only respond to rpm with the c/r bit set to zero 1=only respond to prm with the c/r bit set to one downloaded from: http:///
ds2282 022798 15/22 54016 operation in order to properly operate on t1 lines running the fdl under the definition spelled out in the at&t publication tr 54016, the ds2282 must have the 54016 bit in the ubr set to one (see auser registero). the ds2282 monitors the incoming fdl for maintenance messages from the network. it will decode these messages and re- spond accordingly. the ds2282 will automatically mon- itor the t1 and accumulate the statistics that might be requested from the network. all of the information that is gathered by the ds2282 is locally available to the user. the 54016 register set in the ds2282 mimics the regis- ters defined in tr 54016. when the ds2282 is not re- sponding to maintenance messages, it transmits ffh or 7eh programmed by the control register (cr) of user bits (ub) in the hardware mode. csr: current status register (20) . the 8bit current status register (csr) contains information on whether an unavailable signal state or payload loop- back is active. csr: current status register (20) fu 00 00 l0 (lsb) (msb) f f=1 if either u or l is set to a one u u=1 if an unavailable signal state exists l l=1 if the payload loopback (plb) is active esfeer: esf error event register (21) . a 16bit register that counts esf error events. each esf is checked for the occurrence of an error event. an error event is defined as the logical or'ing of crc6 error events and out of frame (oof) events. a crc6 error event occurs when the locally calculated crc6 code does not match the incoming crc6 code. an oof event occurs when 2 out of 4 consecutive framing bits are received in error. ueeer: user esf error event register (36) . a 16bit register that mimics the esf error event register (esfeer). unlike the esfeer, the ueeer is user clearable once saturated by network error events. this simplifies operations when user registers are created external from the ds2282. cit: current interval timer (22) . a 16bit register that counts the number of seconds in the current 15 min- ute interval. since there can only be 900 seconds in a 15 minute interval, this register will never saturate. since all of the time intervals in the ds2282 are derived from the t1 source, the accuracy of this timer depends on the accuracy of the rclk signal. current interval registers the current interval registers count the number of events that have occurred in the current 15 minute inter- val. there are five separate current interval registers. they are: ciesr (23) counts errored seconds (es) ciuasr (24) counts unavailable seconds (uas) cibesr (25) counts bursty errored seconds (bes) cisesr (26) counts severely errored seconds (ses) cicslfr (27) counts controlled slip seconds (css) and loss of frame counts (lofc) each of these current interval registers is 16 bits in length. please see a54016 definitionso for definitions of es, uas, bes, ses, css, and lofc. interval count registers the interval count registers are a set of 96 separate 16bit registers that contain the number of events that have occurred in each of the previous 96, individual 15 minute periods. or in other words, the interval count registers contain the performance of the t1 line for the previous 24 hours broken into 15 minute periods. there are five separate interval count registers. they are: esicr (28) contains errored seconds (es) uasicr (29) contains unavailable seconds (uas) besicr (2a) contains bursty errored seconds (bes) sesicr (2b) contains severely errored seconds (ses) cslficr (2c) contains controlled slip seconds (css) and loss of frame counts (lofc) please see a54016 definitionso for definitions of es, uas, bes, ses, css, and lofc. downloaded from: http:///
ds2282 022798 16/22 day count registers the day count registers count the number of events that have occurred in the previous 24 hour period. there are five separate day count registers. they are: esdcr (2d) counts errored seconds (es) uasdcr (2e) counts unavailable seconds (uas) besdcr (2f) counts bursty errored seconds (bes) sesdcr (30) counts severely errored seconds (ses) cslfdcr (31) counts controlled slip seconds (css) and loss of frame counts (lofc) each of these current interval registers are 16 bits in length. please see a54016 definitionso for definitions of es, uas, bes, ses, css, and lofc. vitr: valid interval total register (32) . an 8bit register that counts the number of 15 minute intervals since the last reset. hence, it has a maximum count of 96. rmsr: request message status register(33) . an 8bit register that indicates which (if any) re- quest maintenance message has been received. if a re- quest maintenance message is received, the int pin will be asserted (transitions low). the rmsr will be cleared when read. this indicates to an external con- troller that a request has been received and is being pro- cessed. the int pin will return high as soon as the rmsr is accessed. there are currently 15 request messages defined. rm7 rm6 rm5 rm4 rm3 rm2 rm1 rm0 (lsb) (msb) rm7 msb of the request message rm0 lsb of the request message cr: control register (34) . an 8bit register that selects whether the ds2282 will respond to address a (or z) or address b (or y). the default is for the ds2282 to respond only to address a (or z). the user can set the ds2282 to respond address b (or y) by setting the ad bit to a one. in addition, cr allows the user to send an all one's sequence ffh or lapd idel code 7eh. 0 0 0 0 0 0 ics ad (lsb) (msb) ad address select bit. set to a one to re- spond to address b (or y) ics idle code select 0 = ffh 1 = 7eh 54016 definitions errored seconds (es) : a onesecond period with ei- ther: a. one or more crc6 error events or b. one or more oof events or c. one or more controlled slips. severely errored seconds (ses) : a onesecond peri- od with either: a. 320 or more crc6 error events orb. one or more oof events. unavailable seconds (uas) : a onesecond period in which an unavailable signal state is present. in counting uas, the initial period of 10 consecutive ses's is in- cluded in the count whereas the final 10 seconds of 10 consecutive nonses's which removes the unavailable signal state is not included in the count. during uas's, neither es, or ses, or bes, are counted. refer to amonitor registerso for a more detailed description of uas. unavailable signal state : an unavailable signal state is declared when 10 consecutive sess have been re- ceived. an unavailable signal state is considered cleared when 10 consecutive nonses events have oc- curred. controlled slip seconds (css ): a onesecond period with one or more controlled slips. a controlled slip is the deletion or replication of a ds1 frame. indications of controlled slips are input to the ds2282 via the slip pin. if indications of controlled slips are not available, theslip pin should be tied low. downloaded from: http:///
ds2282 022798 17/22 loss of frame count (lofc) : a count of the number of times loss of frame (lof) has been declared. anlof is declared by the following method. each super- frame (3 ms) will be examined for a lof event. if an event is present, then an internal counter (which is not available to the user) will be incremented by five, if no event is present, then the counter will be decremented by one. when the counter crosses a boundary of 4166 (2.5 sec x 333.3 sf/sec x 5 counts/sf) then a lof will be declared and the lofc will be incremented by one. at this point, the counter will be reset to zero when for at least one full second, a lof has not occured. bursty errored seconds (bes) : a onesecond period with more than one but less than 320 crc6 error events. esf error event : each esf is checked for either a crc6 event or an oof event. initializing the address of the serial port the serial port on the ds2282 can be assigned an ad- dress from 0 to 30 decimal. address location 31 decimal will set the serial port into a mode where the extra bit is not needed in the communications over the serial port (see aserial port operationo). the default address is 0 decimal. the ds2282 is shipped from the factory with the default value in place. the address can be pro- grammed in the following manner: 1. power down the ds2282. 2. set the program address select pin to be pulled high when power is applied. 3. configure the user bits 1 to 5 with the desired ad- dress; ub1 is the lsb, ub5 is the msb. 4. leave all other pins open. 5. apply power to the ds2282 for at least 1 second. 6. power down the ds2282. 7. set the program address select pin to remain low when power is reapplied. at this point, the ds2282 will be programmed to the proper value. assigning a new address value can be performed with the same procedure. the address value is stored in nonvolatile memory. nonvolatile storage the ds2282 can retain its onboard program and the contents of the nonvolatile registers for at least ten years in the absence of power at room temperature. if power is applied to the ds2282 at least 50% of the time, the nonvolatile storage will last at least 20 years. single inline connector the ds2282 is designed to connect directly into a 30position single inline connector. these connec- tors are available from a number of vendors. loopback control register the loopback control register (lbcr) allows the user to determine the action of the payload loopback (plb) and line loopback (llb) pins. the user has the option to either allow the ds2282 to respond normally to loop- backs, as described in areceive unscheduled message operation,o or to force the plb or llb pins high or low. the default value for the lbcr is 00 hex. in addition, the lcr allows the user to automatically interrupt the trans- mission of the yellow alarm to either send a prm (t1.403) or a response messagerm (54016) by set- ting the iya bit. the yellow alarm interrupt routine trans- mits 27 opening flags to insure synchronization by the far end receiver prior to transmitting a prm or rm. within the t1.403 mode, an unscheduled message enabled by the tumr register will override the trans- mission of the interruptable yellow alarm. also, the lbcr allows a software method of disabling local slip indications by setting the ds bit. this enables the enhanced configuration data response (model #3) to be sent in 54016 mode, when local slip indication is dis- abled. 0 ds iya 0 dllb fllb dplb fplb (lsb) (msb) ds disable local slip indications. 0 = follow the slip pin for slip indications (this includes disabling slip counts by per- manently tying the slip pin low) 1 = force the disabling of local slip indica- tions regardless of the slip pin iya interruptable yellow alarm enable. 0 = do not transmit an interruptable yellow downloaded from: http:///
ds2282 022798 18/22 alarm 1 = transmit an interruptable yellow alarm dllb disable automatic llb action. 0 = allow the llb pin to act normally 1 = force the llb pin to the value in fllb fllb force llb. 0 = force the llb pin low 1 = force the llb pin high dplb disable automatic plb action. 0 = allow the plb pin to act normally 1 = force the plb pin to the value in fplb fplb force plb. 0 = force the plb pin low 1 = force the plb pin high hardware mode the ds2282 provides an optional hardware mode for operation without an external controller. the external ub5 pin allows the user to select between the hardware and software operating modes. the hardware mode is provisioned by connecting the ub5 pin to gnd. if the ub5 pin is left floating, the software mode is enabled for serial port operations. in the hardware mode, the ds2282 will continue to monitor and supply the fdl data stream messages automatically without any inter- action by the user. b8zs, t1.403, and 54016 operating modes are configured by external pin connections, along with the prm c/r bit control, address, and idle code selects indicated by the hardware mode table. the external ub pins (16) are read during power up or reset events. after power up or reset occurs, the defined hardware operating mode can be changed in software via the corresponding register bits. hardware mode table 7 pin symbol register bit description 24 ub5 n/a 0 (gnd) = hardware select, n/c (floating) = software select 20 b8zs ubrb8zs b8zs select pin . 1 = enabled, 0 = disabled 19 ub4 ubr54016 mode select pin . 0 (gnd) = t1.403, n/c (floating) = tr54016 16 ub1 parrc/r receive prm c/r bit control pin for t1.403 mode . 0 (gnd) = only respond to prm with c/r bit set to one. n/c (floating) = only respondto prm with c/r bit set to zero. crad address select bit control pin for tr54016 . 0 (gnd) = respond to address b (or y). n/c (floating) = respond to address a (or z). 16 ub2 partc/r transmit prm c/r bit control pin for t1.403 mode . 0 (gnd) = force c/r bit to one in outgoing prm. n/c (floating) = force c/r bit to zeroin outgoing prm. crics idle code select bit control pin for tr54016 . 0 (gnd) = 7e (h) n/c (floating) = ff (h). downloaded from: http:///
ds2282 022798 19/22 absolute maximum ratings* voltage on any pin relative to ground 0.3v to v cc operating temperature 0 c to +70 c storage temperature 0 c to 70 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 v ih 2.0 v cc +0.3 v 3 logic 1 for rst v ih 3.5 v cc +0.3 v logic 0 v il 0.3 +0.8 v supply v dd 4.75 5.25 v capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 30 pf output capacitance c out 50 pf dc electrical characteristics (0 c to 70 c; v dd =5v 5%) parameter symbol min typ max units notes supply current i dd 30 ma 1 static input leakage i i 50 +50 m a 2, 3 output voltage (80 m a) v oh 2.4 4.8 v output voltage (1.6 ma) v ol 0.15 0.45 v rst pulldown resistance r pd 40 125 k w notes: 1. rclk=1.544 mhz; v dd =5.25v; outputs open; inputs tied low 2. v in =.45 volts 3. does not apply to rst downloaded from: http:///
ds2282 022798 20/22 ac electrical characteristics (0 c to 70 c; v dd =5v 5%) parameter symbol min typ max units notes rclk period t p 648 ns 1 rclk pulse width t wh , t wl 100 ns rpos, rneg setup to rclkfalling t sd 50 ns rpos, rneg hold from rclkfalling t hd 50 ns propagation delay from tlclk falling to tlink valid t pd 120 m s tlclk period t tp 250 m s 1 tlclk pulse width t th , t tl 50 m s rst pulse width t rst 10 m s slip pulse width t pw 10 m s sync/reframe time 30 ms 2 notes: 1. must be accurate to 32 ppm for precise one second interval measurements. 2. time necessary to sync to an errorfree signal. downloaded from: http:///
ds2282 022798 21/22 ac timing diagram figure 5 slip t p t wh t wl t sd t hd t tp t th t tl t pd t rst t pw rclk rpos, rneg tlclk tlink rst downloaded from: http:///
ds2282 022798 22/22 ds2282 t1 fdl controller/monitor f g h c a b e d j side b side a o n p dim min max 30-pin pkg a in. b in. c in. d in. e in. f in. g in. h in. j in. 3.455 3.505 3.229 3.239 0.845 0.855 0.395 0.405 0.245 0.255 0.075 0.085 0.295 0.305 0.120 0.130 n in. 0.200 0.100 bsc o in. 0.145 p in. 0.054 i i in. 2.900 bsc downloaded from: http:///

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